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mini_projet_hcl/y86simulator--2022-04-06--16-42.json
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{
"editor" : " .pos 0\n # init stack\n irmovl stack, %esp\n # push troisieme argument de la fonction => la taille a copier\n irmovl 5, %eax\n pushl %eax\n # push du deuxieme argument de la fonction => adresse source de la copie\n irmovl t, %eax\n pushl %eax\n # push du premier argument de la fonction => adresse destination de la copie\n irmovl n, %eax\n pushl %eax\n call strncpy\n # clean memory\n iaddl 12, %esp\n halt\n \nstrncpy:mrmovl 12(%esp), %ecx # recuperer le dernier element\n irmovl 0, %ebp\nfor: iaddl 1, %ebp\n mrmovl 4(%esp), %eax # recuperer le premier element\n mrmovl 8(%esp), %edx # recuperer le dernier element\n rrmovl %ebp, %edi\n # multiplier le compteur par la taille d'un element du tableau (4 ici)\nmult4: isubl 1, %edi\n jle next4\n iaddl 4, %eax\n iaddl 4, %edx\n jmp mult4\n # enregistrer la valeur du tableau t a la poistion edx dans le tableau n a la position eax (\nnext4: mrmovl (%edx), %esi\n rmmovl %esi, (%eax)\n andl %esi, %esi\n je end\n iandl 0,%esi\nnext: loopne for\n ret\n\nend: iaddl 1,%esi\n jmp next\n\n .pos 0x100\nt: .long 5\n .long 0\n .long 10\n .long 11\n .long 25\nn:\n .pos 0x200\nstack:\n",
"machineState" : {
"kernel" : "0",
"compilationResult" : {"output":" 0x0000: | | .pos 0 \n | | # init stack\n 0x0000: 30f400020000 | | irmovl stack,%esp \n | | # push troisieme argument de la fonction => la taille a copier\n 0x0006: 30f005000000 | | irmovl 5,%eax \n 0x000c: a00f | | pushl %eax \n | | # push du deuxieme argument de la fonction => adresse source de la copie\n 0x000e: 30f000010000 | | irmovl t,%eax \n 0x0014: a00f | | pushl %eax \n | | # push du premier argument de la fonction => adresse destination de la copie\n 0x0016: 30f014010000 | | irmovl n,%eax \n 0x001c: a00f | | pushl %eax \n 0x001e: a12a000000 | | call strncpy \n | | # clean memory\n 0x0023: c0f40c000000 | | iaddl 12,%esp \n 0x0029: 10 | | halt \n | | \n 0x002a: 41140c000000 | | strncpy: mrmovl 12(%esp),%ecx # recuperer le dernier element\n 0x0030: 30f500000000 | | irmovl 0,%ebp \n 0x0036: c0f501000000 | | for: iaddl 1,%ebp \n 0x003c: 410404000000 | | mrmovl 4(%esp),%eax # recuperer le premier element\n 0x0042: 412408000000 | | mrmovl 8(%esp),%edx # recuperer le dernier element\n 0x0048: 2057 | | rrmovl %ebp,%edi \n | | # multiplier le compteur par la taille d'un element du tableau (4 ici)\n 0x004a: c1f701000000 | | mult4: isubl 1,%edi \n 0x0050: 7166000000 | | jle next4 \n 0x0055: c0f004000000 | | iaddl 4,%eax \n 0x005b: c0f204000000 | | iaddl 4,%edx \n 0x0061: 704a000000 | | jmp mult4 \n | | # enregistrer la valeur du tableau t a la poistion edx dans le tableau n a la position eax (\n 0x0066: 416200000000 | | next4: mrmovl (%edx),%esi \n 0x006c: 406000000000 | | rmmovl %esi,(%eax) \n 0x0072: 6266 | | andl %esi,%esi \n 0x0074: 7385000000 | | je end \n 0x0079: c2f600000000 | | iandl 0,%esi \n 0x007f: 5436000000 | | next: loopne for \n 0x0084: b1 | | ret \n | | \n 0x0085: c0f601000000 | | end: iaddl 1,%esi \n 0x008b: 707f000000 | | jmp next \n | | \n 0x0090: | | .pos 0x100 \n 0x0100: 05000000 | | t: .long 5 \n 0x0104: 00000000 | | .long 0 \n 0x0108: 0a000000 | | .long 10 \n 0x010c: 0b000000 | | .long 11 \n 0x0110: 19000000 | | .long 25 \n 0x0114: | | n: \n 0x0114: | | .pos 0x200 \n 0x0200: | | stack: \n","errors":[],"data":{"_labelToPC":{},"_lineNumberToPc":{},"_pcToLineNumber":{}}},
"cpuState" : {"pc":41,"valP":42,"icode":1,"ifun":0,"ra":15,"rb":15,"valC":0,"valA":0,"valB":0,"srcA":15,"srcB":15,"dstE":15,"dstM":15,"aluA":0,"aluB":0,"valE":0,"cc":0,"bcond":false,"mem_addr":0,"mem_data":0,"mem_read":false,"mem_write":false,"valM":0,"newPC":42},
"registers" : [{"name":"%eax","value_hex":"00000118","value_dec":280},{"name":"%ebx","value_hex":"00000000","value_dec":0},{"name":"%ecx","value_hex":"00000003","value_dec":3},{"name":"%edx","value_hex":"00000104","value_dec":260},{"name":"%esi","value_hex":"00000001","value_dec":1},{"name":"%edi","value_hex":"00000000","value_dec":0},{"name":"%ebp","value_hex":"00000002","value_dec":2},{"name":"%esp","value_hex":"00000200","value_dec":512}],
"flags" : [{"name":"ZF","value":"0"},{"name":"OF","value":"0"},{"name":"SF","value":"0"}],
"status" : [{"name":"STAT","value":"HALT"},{"name":"ERR","value":""},{"name":"PC","value":"00000029"}],
"performance" : [],
"memory" : {"wordSize":4,"startAddress":0,"maxAddress":8192,"words":[{"address":"01fc","value":"05000000"},{"address":"01f8","value":"00010000"},{"address":"01f4","value":"14010000"},{"address":"01f0","value":"23000000"},{"address":"0114","value":"05000000"}]}
},
"hcl" : "####################################################################\n# HCL Description of control for single-cycle y86 processor \"Seq\" #\n# #\n# Original (C) Randal E. BRYANT, David R. O'HALLARON, 2002 #\n# Updates (C) Alexis BANDET, Valentin GAISSET, Romain GUISSET, #\n# Florian SIMBA, 2020 #\n# Updates (C) El Hadji Pathe FALL, Nicolas MARIN PACHE, Corentin #\n# MERCIER, Benjamin MORO, Nathan PRECIGOUT, 2021 #\n####################################################################\n\n## Symbolic representation of y86 instruction codes ################\n\nintsig NOP 'instructionSet.get(\"nop\").icode'\nintsig HALT 'instructionSet.get(\"halt\").icode'\nintsig RRMOVL 'instructionSet.get(\"rrmovl\").icode'\nintsig IRMOVL 'instructionSet.get(\"irmovl\").icode'\nintsig RMMOVL 'instructionSet.get(\"rmmovl\").icode'\nintsig OPL 'instructionSet.get(\"addl\").icode'\nintsig IOPL 'instructionSet.get(\"iaddl\").icode'\nintsig JXX 'instructionSet.get(\"jmp\").icode'\nintsig PUSHL 'instructionSet.get(\"pushl\").icode'\nintsig POPL 'instructionSet.get(\"popl\").icode'\nintsig LOOP 'instructionSet.get(\"loop\").icode'\n\n## Symbolic representation of y86 registers referenced explicitly ##\n\nintsig RECX 'registers.ecx' # ecx register\nintsig RESP 'registers.esp' # Stack Pointer\nintsig REBP 'registers.ebp' # Frame Pointer\nintsig RNONE 'registers.none' # Special value indicating \"no register\"\n\n## ALU functions referenced explicitly #############################\n\nintsig ALUADD 'alufct.A_ADD' # ALU should add its arguments\n\n## Signals that can be referenced by control logic #################\n\n## Fetch stage inputs\nintsig pc 'ctx.pc' # Program counter\n\n## Fetch stage computations\nintsig icode 'ctx.icode' # Instruction control code\nintsig ifun 'ctx.ifun' # Instruction function\nintsig rA 'ctx.ra' # rA field from instruction\nintsig rB 'ctx.rb' # rB field from instruction\nintsig valC 'ctx.valC' # Constant from instruction\nintsig valP 'ctx.valP' # Address of following instruction\n\n## Decode stage computations\nintsig valA 'ctx.valA' # Value from register A port\nintsig valB 'ctx.valB' # Value from register B port\n\n## Execute stage computations\nintsig valE 'ctx.valE' # Value computed by ALU\nboolsig Bch 'ctx.bcond' # Branch test\n\n## Memory stage computations\nintsig valM 'ctx.valM' # Value read from memory\n\n####################################################################\n# Control Signal Definitions. #\n####################################################################\n\n## Fetch stage #####################################################\n\n## Does fetched instruction require a register numbers byte?\nbool need_regids = (\n icode in { RRMOVL, OPL, IOPL, POPL, IRMOVL, RMMOVL } || (icode == PUSHL && ifun == 0));\n\n## Does fetched instruction require a constant word?\nbool need_valC = (\n icode in { IRMOVL, RMMOVL, JXX, IOPL } || (icode == PUSHL && ifun == 1)) || (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4));\n\n## Is instruction valid?\nbool instr_valid =\n icode in { NOP, HALT, RRMOVL, IRMOVL, RMMOVL,\n OPL, IOPL, JXX, PUSHL, POPL} || (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4));\n\n## Decode stage ####################################################\n\n## What register should be used as the A source?\nint srcA = [(\n icode in { RRMOVL, RMMOVL, OPL } || (icode == PUSHL && ifun == 0)) : rA;\n icode == POPL : RESP;\n 1 : RNONE; # Don't need register for reading\n];\n\n## What register should be used as the B source?\nint srcB = [\n icode in { OPL, IOPL, RMMOVL} : rB;\n icode in { PUSHL, POPL } : RESP;\n (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4)) : RECX;\n 1 : RNONE; # Don't need register for reading\n];\n\n## What register should be used as the E destination?\nint dstE = [\n icode in { RRMOVL, IRMOVL, OPL, IOPL } : rB;\n icode in { PUSHL, POPL } : RESP;\n (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4)): RECX;\n 1 : RNONE; # Don't need register for writing\n];\n\n## What register should be used as the M destination?\nint dstM = [\n (icode == POPL && ifun == 0) || (icode == RMMOVL && ifun == 1) : rA;\n 1 : RNONE; # Don't need register for writing\n];\n\n## Execute stage ###################################################\n\n## Select input A to ALU\nint aluA = [\n icode in { RRMOVL, OPL } : valA;\n icode in { IRMOVL, RMMOVL, IOPL } : valC;\n icode in { PUSHL } : -4;\n icode in { POPL } : 4;\n (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4)): -1;\n # Other instructions don't need ALU\n];\n\n## Select input B to ALU\nint aluB = [\n icode in { RMMOVL, OPL, IOPL, PUSHL, POPL } || (icode == LOOP && (ifun == 0 || ifun == 3 || ifun == 4)) : valB;\n icode in { RRMOVL, IRMOVL } : 0;\n # Other instructions don't need ALU\n];\n\n## Set ALU function\nint alufun = [\n icode in { OPL, IOPL } : ifun;\n 1 : ALUADD; # Perform additions by default\n];\n\n## Should condition codes be updated?\nbool set_cc = icode in { OPL, IOPL };\n\nbool is_bch = icode in { JXX } || (icode == LOOP && (ifun == 3 || ifun == 4));\n\n## Memory stage ####################################################\n\n## Set read control signal\nbool mem_read =\n (icode == POPL || (icode == RMMOVL && ifun == 1));\n\n## Set write control signal\nbool mem_write =\n (icode == PUSHL || (icode == RMMOVL && ifun == 0));\n\n## Select memory address\nint mem_addr = [\n icode in { RMMOVL, PUSHL } : valE;\n icode == POPL : valA;\n # Other instructions don't need address\n];\n\n## Select memory input data\nint mem_data = [\n # Value from register\n ((icode == PUSHL && ifun == 0) || (icode == RMMOVL && ifun == 0)) : valA;\n # Return PC address\n (icode == PUSHL && ifun == 1) : valP;\n # Default: Don't write anything\n];\n\n## Program Counter update ##########################################\n\n## Compute address of next instruction to be fetched\nint new_pc = [\n # Call: Use immediate value\n (icode == PUSHL && ifun == 1) || ((icode == LOOP && ifun == 0) && valE != 0) : valC;\n # Taken branch: Use immediate value\n (icode == JXX && Bch) || ((icode == LOOP && ifun == 3) && valE != 0 && Bch) || ((icode == LOOP && ifun == 4) && valE != 0 && !Bch): valC;\n # Completion of RET instruction: Use value retrieved from stack\n (icode == POPL && ifun == 1) : valM;\n # Default: Use incremented PC\n 1 : valP;\n];\n",
"instructionSet" : [
{
"name": "nop",
"icode": 0,
"ifun": 0,
"args": ""
},
{
"name": "halt",
"icode": 1,
"ifun": 0,
"args": ""
},
{
"name": "rrmovl",
"icode": 2,
"ifun": 0,
"args": "rA,rB"
},
{
"name": "irmovl",
"icode": 3,
"ifun": 0,
"args": "valC,rB"
},
{
"name": "rmmovl",
"icode": 4,
"ifun": 0,
"args": "rA,valC?(rB)"
},
{
"name": "rmmovl",
"icode": 4,
"ifun": 0,
"args": "rA,valC"
},
{
"name": "mrmovl",
"icode": 4,
"ifun": 1,
"args": "valC?(rB),rA"
},
{
"name": "mrmovl",
"icode": 4,
"ifun": 1,
"args": "valC,rA"
},
{
"name": "addl",
"icode": 6,
"ifun": 0,
"args": "rA,rB"
},
{
"name": "subl",
"icode": 6,
"ifun": 1,
"args": "rA,rB"
},
{
"name": "andl",
"icode": 6,
"ifun": 2,
"args": "rA,rB"
},
{
"name": "xorl",
"icode": 6,
"ifun": 3,
"args": "rA,rB"
},
{
"name": "sall",
"icode": 6,
"ifun": 4,
"args": "rA,rB"
},
{
"name": "sarl",
"icode": 6,
"ifun": 5,
"args": "rA,rB"
},
{
"name": "jmp",
"icode": 7,
"ifun": 0,
"args": "valC"
},
{
"name": "jle",
"icode": 7,
"ifun": 1,
"args": "valC"
},
{
"name": "jl",
"icode": 7,
"ifun": 2,
"args": "valC"
},
{
"name": "je",
"icode": 7,
"ifun": 3,
"args": "valC"
},
{
"name": "jne",
"icode": 7,
"ifun": 4,
"args": "valC"
},
{
"name": "jge",
"icode": 7,
"ifun": 5,
"args": "valC"
},
{
"name": "jg",
"icode": 7,
"ifun": 6,
"args": "valC"
},
{
"name": "call",
"icode": 10,
"ifun": 1,
"args": "valC"
},
{
"name": "ret",
"icode": 11,
"ifun": 1,
"args": ""
},
{
"name": "pushl",
"icode": 10,
"ifun": 0,
"args": "rA"
},
{
"name": "popl",
"icode": 11,
"ifun": 0,
"args": "rA"
},
{
"name": "iaddl",
"icode": 12,
"ifun": 0,
"args": "valC,rB"
},
{
"name": "isubl",
"icode": 12,
"ifun": 1,
"args": "valC,rB"
},
{
"name": "iandl",
"icode": 12,
"ifun": 2,
"args": "valC,rB"
},
{
"name": "ixorl",
"icode": 12,
"ifun": 3,
"args": "valC,rB"
},
{
"name": "isall",
"icode": 12,
"ifun": 4,
"args": "valC,rB"
},
{
"name": "isarl",
"icode": 12,
"ifun": 5,
"args": "valC,rB"
},
{
"name": "decl",
"icode": 13,
"ifun": 1,
"args": "rA"
},
{
"name": "ncall",
"icode": 10,
"ifun": 1,
"args": "valC"
},
{
"name": "nret",
"icode": 11,
"ifun": 1,
"args": ""
},
{
"name": "loop",
"icode": 5,
"ifun": 0,
"args": "valC"
},
{
"name": "loope",
"icode": 5,
"ifun": 3,
"args": "valC"
},
{
"name": "loopne",
"icode": 5,
"ifun": 4,
"args": "valC"
}
]
}
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